-- Main Sumador        

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.pak_sumador.all;

entity main is
port(p,q: in std_logic_vector(7 downto 0);
     a,b: in std_logic_vector(7 downto 0);
     exp: out std_logic_vector(7 downto 0);
     mantisa: out std_logic_vector(7 downto 0);
	 MAX_O,DIF_O: out std_logic_vector(7 downto 0);
	 sel_o: out std_logic;
	 MAY_O,MEN_O: out std_logic_vector(7 downto 0);
	 DESPLD_O: out std_logic_vector(7 downto 0);
	 SUM_O: out std_logic_vector(7 downto 0);
	 CONT_O: out std_logic_vector(7 downto 0)
);
end main;

architecture behavior of main is
signal rest_dif: std_logic_vector(7 downto 0);
signal rest_max: std_logic_vector(7 downto 0);
signal rest_sel: std_logic;
signal sel_menor_exp: std_logic_vector(7 downto 0);
signal sel_mayor_exp: std_logic_vector(7 downto 0);
signal despld_out: std_logic_vector(7 downto 0);
signal sumar_out: std_logic_vector(7 downto 0);
signal cont_out: std_logic_vector(7 downto 0);
begin
rest_exp1: restador port map(p,q,rest_dif,rest_max,rest_sel);
dif_o <= rest_dif;
max_o <= rest_max;
sel_o <= rest_sel;
selec: selector port map(a,b,rest_sel,sel_menor_exp,sel_mayor_exp);
may_o <= sel_mayor_exp;
men_o <= sel_menor_exp;
despld: desplazadord port map(sel_menor_exp,rest_dif,despld_out);
despld_o <= despld_out;
sum: sumar port map(despld_out,sel_mayor_exp,sumar_out);
sum_o <= sumar_out;
cont: contador port map(sumar_out,cont_out);
cont_o <= cont_out;
rest_exp2: restador2 port map(rest_max,cont_out,exp);
despli: desplazadori port map(sumar_out,cont_out,mantisa);
end behavior;
